The present invention relates to a method for testing a semiconductor memory device and to a semiconductor memory device, particularly to a method for testing a semiconductor memory device having a plurality of memory cells, each of them assigned a unique address beforehand, redundant cells equivalent to the memory cells and replaceable with the memory cells, and a redundancy repair function mode for replacing a predetermined memory cell with the redundant cell, and a semiconductor memory device applicable to the method.
A semiconductor memory device is provided with a memory array having a plurality of memory cells (so-called cells) two-dimensionally arranged. Even a single defective memory cell (hereafter, it is called defective cell) is in the memory array, and then the device is turned to be a defective piece. On this account, the semiconductor memory device is generally provided with a redundant memory having a plurality of spare memory cells (so-called redundant cells) arranged beforehand for replacing a defective cell generated at fabrication process steps with a redundant cell to improve fabrication yields (so-called redundancy repair). This replacement is conducted by the row or column in which a word line or bit line in the redundant memory is selected instead of selecting a word line or bit line corresponding to a defective cell in the memory cells. Hereafter, selecting a word line in the redundant memory instead of a word line in the memory cells is referred to as row replacement, and selecting a bit line in the redundant memory instead of a bit line in the memory cells is referred to as column replacement. Traditionally, in a semiconductor memory device (device) having a redundancy repair function, access first has been made to each of the memory cells inside the address space of the device, that is, inside the cell area, and an operation test has been conducted to verify each of the memory cells to be normal or not. When the operation test has found a defective cell, row replacement or column replacement has been performed as described above to replace the defective cell with a redundant cell, and the operation test has been again conducted. Then, device chips verified to be normal at the first test and device chips verified to be normal at the retest have been cut out of a wafer for packaging.
However, according to this method, a redundant cell will not be verified to be defective or not until it is replaced with a defective cell. Therefore, there has been a problem that redundancy repair cannot be done when the replaced redundant cell may be defective.
In addition, it is also possible that redundant cells are replaced at arbitrary addresses in the cell area so as to be accessible to the redundant cells, and then the redundant cells also undergo the operation test to replace normal redundant cells with defective cells in the memory array. However in this case, the operation test for the cells and the operation test for the redundant cells are conducted independently. Thus, there has been a problem that the time required for the tests is prolonged.